Root-Raised-Cosine (RRC) filters are widely used for the purpose of pulse shaping in many wireless communication systems, such as WCDMA, TDSCDMA, CDMA2000, IS136, PDC and PHS. In these communication systems, the RRC filters are utilized in both transmitters and receivers. Such filters, preferably implemented in the digital domain, typically utilize a sampling rate that is a multiple of the symbol rate or chip rate of the wireless communication system, either to facilitate removal of the image spectrum in the analog domain in the case of transmitters or to ease the design of the analog anti-aliasing filter in the case of receivers. Thus, for example, the filter sampling rate may be eight times (8×) the symbol (or chip) rate of the signal being filtered. As used herein, the notation “8×” expresses the sampling rate as a multiple of the signal symbol (or chip) rate.
A block diagram of a conventional transmitter chain is shown in FIG. 1. The signal to be filtered at a 1× data rate is supplied to an 8× RRC digital filter 10. The output of 8× digital filter 10 is supplied to a digital-to-analog converter (DAC) 12. The output of DAC 12 is supplied an analog low pass filter 14 which performs image rejection. In other embodiments, a 24× RRC digital filter is utilized.
A block diagram of a conventional receiver chain is shown in FIG. 2. The analog signal to be filtered is input to an anti-aliasing filter implemented as an analog low pass filter 20. The output of filter 20 is supplied to an analog-to-digital converter (ADC) 22 which samples the analog signal at an 8× sampling rate. The 8× signal is supplied to an 8× RRC digital filter 24. In other embodiments, ADC 22 has a 4× sampling rate and/or filter 24 is a 4× RRC digital filter.
Conventional systems have utilized a so-called direct digital implementation, wherein the filter is implemented as a digital filter having the desired sampling rate. Thus, for example, an 8× filter would be implemented as an 8× RRC digital filter. However, such filter implementations require a large number of filter coefficients, since the number of coefficients required is proportional to the sampling rate, and are complex as well. Consequently, such filter implementations consume a relatively large amount of power and silicon area.
According to the sampling theory, a 2× rate (twice the chip or symbol rate) is sufficient for the ADC, the DAC, and the RRC filters. However, such a low over-sampling rate would put very stringent requirements on the analog anti-aliasing (channel selection) filter in the receiver path and the image rejection filter in the transmitter path. Using a higher over-sampling rate, such as an 8× rate, in the RRC filter makes the design of the analog filters much easier.
Accordingly, there is a need for new and improved filter configurations and methods which enable conflicting requirements to be satisfied.